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? freescale semiconductor, inc., 2005, 2006, 2007, 2008. all rights reserved. freescale semiconductor product preview this document contains information on a product under developm ent. freescale reserves the right to change or discontinue this product without notice. document number: mc1322x rev. 1.7 06/2008 mc13224v package information case 1901-01 99-pin [9.5x9.5x1.2mm] ordering information device device marking package mc13224v 1 1 see table 1 for more details. 13224v lga MC13224VR2 1 13224v lga 1 introduction the mc13224v is freescale? s third-generation zigbee platform which incorporat e a complete, low power, 2.4 ghz radio frequency transc eiver, 32-bit arm7 core based mcu, hardware accel eration for both the ieee 802.15.4 mac and aes security , and a full set of mcu peripherals into a 99-pin lga platform-in-package (pip). the mc13224v solution can be used for wireless applications ranging from simple proprietary point-to-point connectivity to complete zigbee mesh networking. the mc13224v is designed to provide a highly integrated, total solution, with premier processing capabilities and very low power consumption. the mc13224v mcu resources offer superior processing power for zigbee ap plications. a full 32-bit arm7tdmi-s core operates up to 26 mhz. a 128 kbyte flash memory is mirrored into a 96 kbyte ram for upper stack and applications software. in addition, an 80 kbyte rom is available for boot software, standardized ieee 802.15.4 mac and mc13224v advanced zigbee ? - compliant platform-in-package (pip) for the 2.4 ghz ieee ? 802.15.4 standard contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4 mcu peripherals . . . . . . . . . . . . . . . . . . . . . . 15 5 pin assignments and connections . . . . . . 24 6 system electrical specification . . . . . . . . . 32 7 developer environment . . . . . . . . . . . . . . . . 44 8 preliminary mech anical diagrams (case 1901-01, non-jedec) . . . . . . . . . . . . 46
mc13224v product preview, rev. 1.7 2 freescale semiconductor communications stack software. a fu ll set of peripherals and direct memory access (dma) capability for transceiver packet data complement the processor core. the rf radio interface provides for low cost and the high density as shown in figure 1 . an onboard balun along with a tx/rx switch allows di rect connection to a single-ended 50- antenna. the integrated pa provides programmable output power typically from -30 dbm to +4 dbm, and the rx lna provides -95 dbm sensitivity. in addition, sepa rate complementary pa outputs allo w use of an external pa and/or an external lna for extended range applications. the device also has onboa rd bypass capacitors and crystal load capacitors for the smal lest footprint in the industry. all components are integrated into the package except the crystal and antenna. figure 1. mc13224v rf radio interface in addition to the best-in-class mcu performance and power , the mc13224v also pr ovides best-in-class power savings. typical transmit or receive current is 20 ma with the cpu at 2 mhz operation and even lower with the bus steali ng enabled. onboard power supply regulat ion is provided for source voltages from 2.0 vdc to 3.6 vdc, and the source vol tage can be as low as a regulated 1.8 vdc if the non-volatile memory is powered directly from the source. numerous low current modes are available to maximize battery life including sleep or restrict ed performance operation. applications include, but are not limited to, the following: ? residential and commercial automation ? lighting control ? security ? access control ? heating, ventilation, air-conditioning (hvac) ? automated meter reading (amr) ? industrial control analog transmitter analog receiver rf tx/rx switch balun lna pa
mc13224v product preview, rev. 1.7 freescale semiconductor 3 ? asset tracking and monitoring ? homeland security ? process management ? environmental mon itoring and control ?hvac ? automated meter reading ? health care ? patient monitoring ? fitness monitoring ? consumer ? remote control ? entertainment systems ? cellular phone attach 1.1 ordering information table 1 provides additional details about the mc13224v table 1. orderable parts details device operating temp range (ta.) package memory options description mc13224v -40 to 105 c lga 96kb ram, 128kb flash intended for 802.15.4 standar d compliant applications, freescale 802.15.4 mac, and freescale beestack. MC13224VR2 -40 to 105 c lga tape and reel
mc13224v product preview, rev. 1.7 4 freescale semiconductor 2features this section provides a simplified block diagram and highlights mc13224v features. 2.1 block diagram figure 2 shows a simplified block diagram of the mc13224v. figure 2. mc13224v simplified block diagram 2.2 features summary ? ieee 802.15.4 standard complian t on-chip transceiver/modem ? 2.4 ghz ism band operation ? 16 selectable channels ? programmable transmitter output pow er (-30 dbm to +4 dbm typical) ? world-class receiver sensitivity ? < -96 dbm typical receiver sensitivity using dcd mode (<1% per, 20-byte packets) ? < -100 dbm typical receiver sensitivity us ing ncd mode (<1% per, 20-byte packets) ? hardware acceleration fo r ieee 802.15.4 applications ? mac accelerator (seque ncer and dma interface) timer module (tmr) (4 tmr blocks) uart module (uart0) uart module (uart1) sync serial interface (ssi/i2s) keyboard interface (kbi) inter-ic bus module (i2c) serial peripheral interface (spi) dual 12-bit adc module gpio and io control up to 64 io pins arm7 tdmi-s 32-bit cpu bus interface & memory arbitrator arm interrupt controller (aitc) jtag/ nexus debug advanced security module (asm) clock & reset module (crm) radio interface module (rif) 96kbyte sram (24k words x 32 bits) 80kbyte rom (20kwords x 32 bits) rf oscillator & clock generation spi flash module (spif) 802.15.4 mac accelerator (maca) digital modem tx modem rx modem 128kbyte non-volatile memory (serial flash) analog transmitter analog receiver rf tx/rx switch ieee 802.15.4 transceiver balun analog power management & voltage regulation mc13224v buck regulator 24 mhz (typ) 32.768 khz (optional) battery detect
mc13224v product preview, rev. 1.7 freescale semiconductor 5 ? advanced encryption/decryption hardware engine (aes 128-bit) ? supports standard ieee 802.15.4 si gnaling with 250 kbps data rate ? 32-bit arm7tdmi-s cpu core with programmable performanc e up to 26 mhz (24 mhz typical) ? extensive on-board memory resources ? 128 kbyte serial flash memory (will be mirrored into ram) ? 96 kbyte sram ? 80 kbyte rom ? best-in-class power dissipation ? 21ma typical rx current draw (dcd mode) with radio and mcu active ? 28 ma typical tx current draw with radio and mcu active (coin cell capable) ? 5ma maximum current draw with mcu active (radio off) ? 0.9ma maximum current with mcu idle (radio off) ? 1.1 a maximum hibernate current (r etain 8 kbyte sram contents) ? 0.3 a maximum off current (device in reset) ? extensive sleep mode control and variation ? hibernate and doze low power modes ? programmable degree of power down ? clock management ? onboard 2khz oscillator for wake-up timer. ? optional 32.768 khz crystal oscill ator for accurate real-time sl eep mode timi ng and wake-up with a possible sleep period greater than 36.4 hours ? wake-up through programmable timer, extern al real-time interrupts, or adc timer ? extensive mcu peripherals set ? dedicated 802.15.4 modem/radio interface module (rif) ? dedicated nvm spi interface for managing flash memory ? two dedicated uart modules capable of 2mbps with cts/rts support ? spi port with programmable master and slave operation ? 8-pin keyboard interface (kbi) supports up to a 4x4 matrix. also, provides up to 4 asynchronous interrupt inputs for wake-up ? two 12-bit analog-to-digital convert ers (adcs) share 8 input channels ? four independent 16-bit timers with pwm capa bility. these can cascade in combinations up to 64-bit operation ? inter-integrated circuit (i 2 c) interface ? synchronous serial interface (ssi) with i 2 s and spi capability and fifo data buffering ? up to 64 programmable i/o sh ared by peripherals and gpio ? powerful in-circuit debug and flash pr ogramming available via on-chip debug ports ? jtag debug port ? nexus extended feature debug port
mc13224v product preview, rev. 1.7 6 freescale semiconductor ? system protection features ? low battery detect ? watchdog timer (cop) ? sleep mode timer ? low external component count ? only antenna needed for single-ended 50- rf interface (balun in package) ? only a single crystal is required for the main os cillator; programmable cr ystal load capacitors are on-chip ? all bypass capacitors in package ? supports single crystal reference clock source (typical 24 mhz crystal with 13 - 26 mhz usable) with on-chip programmable crystal load capacita nce or external frequenc y source. also provides onboard 2khz oscillator for wake-up timing or an optional 32.768 khz crystal for accurate low power timing. ? 2.0v to 3.6v operating voltage w ith on-chip voltage regulators; down to 1.8v with off-chip regulation ? optional buck converter fo r better battery life. ? -40c to +105c temperature range ? rohs-compliant 9.5mm x 9.5mm x 1.2mm 99-pin lga package 2.3 high density, low component count, integrated ieee 802.15.4 solution the mc13224v is more than a high performance, low power platform-in-a-package ieee 802.15.4 solution. not only are the transceiver (radio) and mc u on an soc, the packaged solution contains a 128 kbyte serial flash memory, onboard bypass capaci tors for critical nodes, and rf components that present a single-ended 50- interface for an external antenna. the ra dio is a full differential design with an on-chip transmit/receive (tx/rx ) switch, and the pip also has an onboard balun for differential to singled-ended conversion. on-chip rf matching is also provided to present the proper impedance to the antenna. to further simplify the applicati on, single crystal operation (optimized for 24 mhz) is supported for full radio and mcu operation. if the default 24 mhz cr ystal is not used, the device supports 13-26 mhz crystals also. the load capacitance to the crystal oscillator is supplied on- chip to eliminate the need for the otherwise required external capacitors. 2.4 integrated ieee 802.15.4 transceiver (radio and modem) the mc13224v ieee 802.15.4 fully-complia nt transceiver provides a co mplete 2.4 ghz radio with 250 kbps offset-quadrature phase shift keying (o-qpsk) data in 5.0 mhz ch annels and full spread-spectrum encode and decode. the modem s upports transmit, receive, clear ch annel assessment (cca), energy detect (ed), and link quality indicati on (lqi) as required by the 802.15.4 standard.
mc13224v product preview, rev. 1.7 freescale semiconductor 7 2.4.1 rf interface and usage the mc13224v rf interface pr ovides for a single-ended, 50- port that connects dir ectly to an antenna. there is an onboard balun that conve rts the single-ended interface to a full differential , bi-directional, on-chip interface with tran smit/receive switch, lna, and complementary pa outputs. the required port impedance matching is also onboard. this combination allows for a very small footprint and a very low cost rf solution. the receiver demodulator includes a module called the differential ch ip detector which has two modes of operation: ? non-coherent detection (ncd) with automatic frequency control (afc) ? non-coherent differential chip detection (dcd) without afc ieee 802.15.4 standard allows a maximum clock drift of 40 ppm (which equals 80 ppm station-to-station). the mc13224v 802.15.4 demodulator includes two di fferent methods of operating in the presence of such large frequenc y errors, i.e., ncd and dcd. with dcd mode, rx performance loses ~3.5 db of sensitivity. alternatel y, ncd mode provides an increased ~3.5 db of sensi tivity, however, the addition of the afc increases the dem odulator current drain about 3-4 ma. for longer range applications where external amplification may be desi red (lna and/or pa), additional ports are provided for secondary comp lementary pa outputs. these can be used as a separate pa interface while the single-ended port through the ba lun is used as an input only. al so, 4 control pins and a regulated 20 ma voltage source are provided to control extern al components and supply power to the pa outputs. the rf interface functionality can be summarized as follows: ? programmable output power ? 0 dbm nominal output power, program mable from -30 to +4 dbm ? receive sensitivity (at 1% per, 20-byte packet) - ? < -96 dbm (typical) dcd re ceive (well above ieee 802.15.4 specification of -85 dbm) ? < -100 dbm (typical) ncd receive (higher current) ? single-ended 50- antenna port ? uses integrated tran smit/receive (t/r) switch, lna, and onboard balun. impedance matching onboard. ? maximum flexibility ? optionally, single-ended por t becomes rf input only and a separate set of full differential pa outputs are provided. separa te input and outputs allo w for a variety of rf configurations including external lna and pa for increased range ? four control signals for external rf components such as a lna or pa ? regulated voltage source for pa bias ing and powering external components 2.4.2 modem the modem supports the full require ment of the ieee 802.15.4 standard to transmit and receive data packets. in additional, the mechanism is present to measure received signal leve l to provide cca, ed, and lqi as required by the 802.15.4 standard.
mc13224v product preview, rev. 1.7 8 freescale semiconductor 2.5 high performance, low power 32-bit arm7 processor ? the arm7tdmi-s processor is a member of the 32-bit arm family of general-purpose 32-bit microprocessors that offers high perform ance with very low-power consumption ? a three stage instruction pipeline (fetch, decode , execute) increases the speed of the flow of instructions to the processor ? data access can be 8-bit bytes, 16-bit half words, or 32-bit words. words must be aligned to 4-byte boundaries. half words must be aligned to 2-byte boundaries ? the arm7tdmi-s processor supports two instruct ion sets, i.e., the 32-bit arm instruction set and the 16-bit thumb instruction se t. the thumb mode incorporates 16-bit instructions for higher code density while retaining all th e benefits of a 32-bit architecture, i.e., full 32-bit registers, 32-bit operations, and 32-bit memory tran sfer. the use of the instructi on sets can be intermixed for maximizing performance while re taining higher code density figure 3. arm7tdmi-s 32-bit cpu core register bank 31 x 32-bit registers (6 status registers) address register address incrementer incrementer bus pc bus addr[31:0] 32 x 8 multiplier alu bus scan debug control barrel shifter 32-bit alu a bus write data register instruction pipeline read data register thumb instruction decoder wdata[31:0] rdata[31:0] instruction decoder and control logic b bus
mc13224v product preview, rev. 1.7 freescale semiconductor 9 2.6 low power operation and power management the mc13224v is inherently a very low power device, but it also ha s extensive power management and an onboard buck regulator opti on to maximize battery life. 2.6.1 operating current the mc13224v operating currents ar e a function of operating mode. there are two basic low power modes of hibernate and doze, and both have options of how much ram contents are retained. the difference between hibernate and do ze is that doze mode keeps the primary refe rence oscillator running. highest operating current is when the radio is active for transmit or receive. refer to section 6.4, ?supply current characteristics? for more details and specifications. 2.6.2 power management the mc13224v power management is controlled th rough the clock and reset module (crm). the crm is a dedicated module to handle mcu clock, reset, and power management functions which includes control of the power regulators. all these func tions have impact on attaining lowest power. 2.6.2.1 crm features the crm features include: ? control of system reset ? control clock gating for power savings ? sleep mode (hibernate and doze) management ? degree of chip power down ? retention of programmed parameters ? programmable retention of ram contents ? clock management ? wake-up management ? graceful power-up ? clock management ? wake-up via programmable tim er or external interrupts. ? wake-up timer ? for hibernate mode, based on onboard 2 kh z oscillator or optional 32.768 khz crystal oscillator ? for doze mode, based on main refe rence oscillator, typically 24 mhz ? controls reference clocks based on default 24 mhz crystal oscillator or optional 13-26 mhz oscillator with pll (external filt er) for 24 mhz frequency synthesis. ? mcu watchdog timer (cop) ? software initiated reset
mc13224v product preview, rev. 1.7 10 freescale semiconductor ? management control of onboard linear regulators and optional buck regulator 2.6.2.2 crm operation the crm has primary control of the entire system: ? reset and power up ? after release of the hard ware resetb signal, the crm will perform a power up sequence of the mcu. the linear regulators and clock sour ces are managed for a graceful start-up of the mcu and its resources. the radio is not powered until needed ? normal operation of mcu ? the cl ock management of the mcu and its resources are controlled by the crm. the processor clock is programma ble from low frequencies up to the maximum reference frequency (13-26 mhz opti onal w/24 mhz standard) to allow the application to trade-off processing speed versus power savings ? sleep modes and recovery ? there are two sl eep modes of hibernate and doze. the primary difference is that doze mode ke eps the reference oscillator running. both modes can re tain critical programmed parameters and have selectable sizes of ram retent ion. hibernate has lowest power, but doze allows high accuracy sleep timing. th e crm manages the recovery from low power, similar to power-up from reset, provi ding regulator and clock management. ? wake-up can be based on external interrupts through 4 kbi inputs ? wake-up can be from internal interrupts ? wake-up can be based on an rti (wake-up) timer. ? the rti timer with 2 possible frequency sources provides a very low power wake-up option from sleep ? one option is an onboard, lo w accuracy 2 khz oscillator ? a second option is to add an external 32.768 khz crystal for the rti clock source ? a 32-bit timer allows greater than a 36.4 hour wake-up delay with the 32.768 crystal oscillator ? other features of the crm: ? an optional cop watchdog timer to monitor cpu program activity ? a programmable software reset 2.6.3 optional buck regulator for battery based applications, an optional buck re gulator is provided to maximize battery life. figure 4 shows the configuration of the buc k regulator versus the normal connection. an onboard mosfet is used as a switch with an external 100 h inductor and 10 f capacitor when the buck regulator is enabled. the buck regulator drops the higher battery voltage to 1.8 - 2.0 vdc that is applied to the onboard linear regulators. this allows lower net current from the battery to maximize th e life of the battery.
mc13224v product preview, rev. 1.7 freescale semiconductor 11 figure 4. optional buck regulator 2.6.4 battery detect an optional feature of the adc m odule is battery voltage detect. pr ogrammable thresholds are provided for an adc analog sample channel to monitor the battery high voltage and ba ttery low voltage. this feature can be used as a tr igger to provide low batter y indication, protection for da ta that may be lost due to end-of-life for the battery, monitoring ch arging, and controlling buck regulator operation. 2.7 ieee 802.15.4 acceleration hardware the mc13224v provides accelerati on hardware for ieee 802.15.4 applications and this hardware includes 802.15.4 mac acceleration a nd aes encryption/decryption. 2.7.1 802.15.4 mac accelerator (maca) overview the mc13224v contains a hardware bl ock that provides a lo w-level mac and phy lin k controller, which together with software running on th e arm core, implements the baseband protocol s and other low-level link routine control and link control. components of the maca include a se quencer/controller (with timers), tx and rx packet buf fers, dma block, frame check sequence (fcs) generator/checker, and control registers. figure 5 shows a maca simplified block diagram. as part of the 802.15.4 protocol, pack ets are generated and tr ansmitted, packets are re ceived and verified, and channel energy is measured via a clear channel assessment (cca). also, combinations or sequences of events are required as part of the protocol such as an ack respons e following a received packet. the maca facilitates these activ ities via control of the tr ansceiver and off loads the functions from the cpu. a dedicated dma function moves data between the maca buffers and ram on a cycle steal basis and does not require intervention from the cpu. the maca is responsible for constr uction of packets for tx including fcs, and for parsing the received packets. the maca will also handle acks and txpo ll sequences independent of the arm processor. during tx the maca will construct the entire packet. this includes preamble and sfd (start of frame lreg_bk_fb vdd l2 100uh c2 10uf coil_b k vbatt mc13224v vbatt coil_bk lreg_bk_fb vdd nc mc13224v normal operation buck regulator
mc13224v product preview, rev. 1.7 12 freescale semiconductor delimiter). during receive, the modem will recognize preamble a nd sfd, then the maca will begin receiving the packet with the first bit of fr ame length, and finally, will check the fcs. figure 5. mac accelerator si mplified block diagram note the radio can receive packet s of either mode withou t prior indication of the incoming packet mode. 2.7.1.1 maca features in order to reduce cpu lo ad, the maca module has embedded features for co ntrolling parts of the ieee 802.15.4 phy and mac layer requirements. the maca core features include: ? sequence manager sequences / auto sequences ? rx only ? tx only ? automatic acknowledgment frame r eception on transm itted packets ? automatic acknowledgment frame transmission on received packets ? auto-rx for continuous re ception as coordinator ? auto sequence for transmitted mac data.request ? assist for efficient res ponse to mac data.request ? embedded channel assessment in sequence ? support for sequences with slotted mode access ? timer triggered and imme diately executed actions ? support for extended rx for reception in ra ndom backoff and battery life extension ? support for promiscuous mode ? programmable auto sequence timing - each cca, rx, or tx event is an independent operation. the radio gets through a power-up or ?warm-up? sequence for each operation (including vco), tx packet buffer rx packet buffer sequencer timers fcs generator/ checker dma control registers maca to transceiver modem to mcu bus
mc13224v product preview, rev. 1.7 freescale semiconductor 13 and there is also a power-down or ?warm-down? time. sequences are combinations of radio operations and are highly configurable. ? rx warm-up is 72 s ? tx warm-up is 92 s ? turnaround times ? the ieee 802.15.4 standard requires a tx-to-rx or a rx-to-tx tu rnaround time to be less than or equal to 12 symbols times (192 s). ? best practice for maximum station-to-stati on performance is to minimize tx-to-rx turnaround time and to maximize (wit hin spec) rx-to-tx turnaround time. ? auto sequences should use r ecommended turnaround times of: a) 11 symbols times (176 s) rx-to-tx b) 96 s tx-to-rx. ? dedicated dma for transfer of tx/rx data from/to ram (minimum bus clock of 2 mhz for 802.15.4 modem operation) ? maskable, event-driven interrupt generation ? address header filtering for rece ived packets. a promiscuous mode allows bypass of the filtering for monitoring network traffic ? packet manager ? handles preamble data ? handles frame check sequence (fcs) a.k.a crc ? embedded header filter for received packets ? beacon support mode ? control/status registers mapped into cpu memory map ? 32-bit random number generator ? runs at the bus clock rate, a 32-bit li near feedback shift register (lfsr) can be set with a seed value and uses a 32-bit primitive polynomial. a 32-bit random number is fetched with every read of the proper control register 2.7.2 advanced security module (asm) the ieee 802.15.4 standard and the zigb ee standard both provide for opti onal use of data encryption.the asm engine is a hardware block that accelerates encryption/decryption using the advanced encryption standard (aes). the engine can perform ?counter ? (ctr) and cipher block chaining (cbc) encryption. the combination of these two mode s of encryption are known as ccm m ode encryption. ccm is short for counter with cbc-mac. cc m is a generic authenticate and en crypt block cipher mode. ccm is only defined for use with 128 bit block ciphers, such as aes. the definition of ccm mode encryption is documented in the nist publication sp800-38c. the asm has the following features: ? 32-bit wide bus interface ? ctr encryption in 13 clock cycles ? cbc encryption in 13 clock cycles
mc13224v product preview, rev. 1.7 14 freescale semiconductor ? encrypts 128 bits as a unit ? the 128-bit registers are ali gned on quad word boundaries (16 byte) ? self-test mode ? maskable ?action complete? interrupt 3memory the mc13224v memory resources consis t of ram, rom, and serial flash. 3.1 ram and rom the ram and rom features include: ? 96 kbytes ram. ? ram0: 8 kbytes, 2 kwords (2048 x 32 bits) ? ram1: 24 kbytes, 6 kwords (6144 x 32 bits) ? ram2: 32 kbytes, 8 kwords (8192 x 32 bits) ? ram3: 32 kbytes, 8 kwords (8192 x 32 bits) ? all read or write accesses require a minimum of two system clock cycles ? stall signal generated for read after write cycles ? clock is enabled only on the accessed memory device for low power consumption ? rams have been divided to allow for power sa vings. while sleeping, th e above ram blocks can be turned off (combina tions include 8, 32, 64, and 96 kbytes active) and the ra m remainder can be placed in a low voltage mode for data retention. if more ra ms are turned on, then less battery life will be achieved. dependi ng on the amount of ram powered during sleep, the boot time may be longer with less ram as the non-powered ram must be reloaded from flash. ? 80 kbytes rom ? 20 kwords (20480 x 32 bits) ? initially contains bootstrap code, 802.15.4 mac ( no security), uart driver, and spi driver. the mac software builds on the lower level ha rdware capability of the transceiver and maca. all code except the bootstrap is ?patchable?. ? can be extended later to communications st ack software and nvm services (erase, program, and read routines) 3.2 serial flash (nvm) the mc13224v also contains a 128 kbyt e serial flash memory that can be mirrored into the 96 kbyte ram. the serial flash is accessed via an intern al dedicated spi module (spif). the flash erase, program, and read capability are pr ogrammed through the spi f port. the flash is accessed at boot time to load/initialize ram. all actual cpu pr ogram and data access is from ram or rom.
mc13224v product preview, rev. 1.7 freescale semiconductor 15 4 mcu peripherals the mc13224v has a rich set of mcu peripherals. figure 6 shows the peripheral modules. figure 6. mcu peripherals timer module (tm r ) (4 tm r blocks) uart module (u a r t0) uart module (u a r t1) sync serial in te r fa c e (s s i/i2s ) keyboard in te r fa c e (kbi) in te r -ic b u s module (i2c ) serial peripheral in te r fa c e (spi) dual 12-bit adc module gpio and io control up to 64 io pins arm7 tdmi-s 32-bit cpu bus in te r fa c e & memory arbitrator arm interrupt controller (a itc ) jtag/ nexus debug from crm battery detect spi flash module (spif)
mc13224v product preview, rev. 1.7 16 freescale semiconductor 4.1 parallel io (gpio) the parallel i/o features include: ? a total of 64 general-purpose i/o pins ? individual control (direction and output st ate) for each pin when in gpio mode ? pad hysteresis enables ? software-controlled pull-ups/ pull-downs on each input pin ? when not used as gpio, the io provide alternative functions ? debug ports for jtag (four signals) and nexus (fourteen signals) modules ? four control signals for external rf componen ts such as an lna, pa, and antenna switch ? eight analog inputs for adc input channels ? four signals for adc reference voltages ? eight signals for uart1 and uart2 ?two i 2 c signals ? four timer block signals ? four spi block signals ? four ssi block signals ? eight kbi signals ? eight kbi pins are kept alive during hibernate or doze. four kb i are output and four are inputs. the input can be used as wake-up interrupts 4.2 keyboard interface (kbi) the mc13224v designates 8 pins (kbi_0 to kbi_7) as a keyboard interface, where four of these signals typically are outputs and four are inputs (kbi_4 to kbi_7) that suppor t interrupts. these 8 pins could typically be used as a matrix in terface to support up to 16 switches or buttons, such as a keypad. these signals can also be used as general purpose io if a keybo ard is not present. during hibernate or doze, the kbi are unique in that they are kept alive. four kbi are outputs and four kbi are inputs. the inputs can be enabled as asynchronous interrupts to wake-up the mc13224v from the sleep mode.
mc13224v product preview, rev. 1.7 freescale semiconductor 17 4.3 timer (tmr) module the mc13224v provides a timer module (tmr) that contains four iden tical counter/timer groups. each group is capable of many variants of input capture, output compare a nd pulse-width modulation. the wide range of operational modes is useful fo r many control and sensor applications. figure 7 shows a block diagram of an individual timer group. figure 7. timer group block diagram each 16-bit counter/timer gr oup contains a prescaler, a counter, a load register, a hold register, a capture register, two compare registers, and status and control registers. ? load register ? provides the ini tialization value to the counter when the counter?s terminal value has been reached ? hold register ? captures the counter?s value wh en other counters are being read. this feature supports the reading of cascaded counters ? capture register ? enables an external signal to take a snap shot of the counter?s current value ? comp1 and comp2 registers ? provides the values to which the counter is compared. if a match occurs, the oflag signal can be se t, cleared, or toggled. at match time, an interrupt is generated (if enabled), and the new compare value is load ed into the comp1 or comp2 registers from cmpld1 and cmpld2 if enabled cmpld1 comp1 load hold status and control cmpld2 comp2 counter comparator comparator capture m u x prescaler m u x peripheral reference clock other counter reference oflag output external mcu data bus
mc13224v product preview, rev. 1.7 18 freescale semiconductor ? the prescaler provides different time ba ses useful for clocki ng the counter/timer ? the counter provides the ability to count internal or external events ? control and status registers ? provides operationa l mode control of the counter, status, clock source control, interrupt control, and external interface control four gpio pins (tmr0 -tmr3) are programmable and can be used with any counter/timer group. the tmr module feature include: ? four 16-bit counters/timers groups ? up/down count ? counters are cascadable for up to 64 bit delay counter ? programmable count modulo. ? peripheral reference clock equates to reference osci llator frequency ? external clock max count rate equa ls peripheral clock divided by 2 ? internal clock max count ra te equals peripheral clock. ? count once or repeatedly ? counters are preloadable ? compare registers are preloadable ? counters share available 4 gpio pins (programmable as inputs or outputs and programmable for falling or rising edge) ? separate prescaler for each counter ? each counter has capture and compare capability ? optional input glitch filter ? functional modes include stop, count, edge-count, gated-count, quadrature-count, signed-count, triggered-count, one-shot, cascade-count, pulse-output, fixed frequency pwm, and variable-frequency pwm 4.4 uart modules the mc13224v has two universal as ynchronous receiver/tran smitter (uart) modules. each uart has an independent fractional divider, ba ud rate generator that is clocked by the peripheral bus clock (typically 24 mhz) which enables a broad range of baud ra tes up to 1,843.2 kbaud. transmit and receive use a common baud rate for each module. each uart provides the following features: ? 8-bit only data ? one or two stop bits ? programmable parity (even, odd, and none) ? four-wire serial interface (rxd, txd, rts, and cts) ? hardware flow control support for rts and cts signals ? 32-byte receive fifo a nd 32-byte transmit fifo
mc13224v product preview, rev. 1.7 freescale semiconductor 19 ? programmable sense for rts/ct s pins (high true/low true) ? status flags for various fl ow control and fifo states ? receiver detects framing errors, st art bit error, break characters, parity errors, and overrun errors. ? voting logic for improved noise immunity (16x/8x oversampling) ? maskable interrupt request ? time-out counter, which times out after eight non-present characters ? receiver and transmitter enable/disable ? low-power modes ? baud rate generator to provide any multipl e-of-2 baud rate between 1.2 kbaud and 1,843.2 kbaud 4.5 inter-integrated circuit (i 2 c) module the mc13224v provides an in ter-integrated circuit (i 2 c) module for the i 2 c which is a two-wire, serial data (sda) and serial clock (scl), bidirectional serial bus. the i 2 c allows for data ex change between the mc13224v and other devices such as mcus, serial eeprom, serial adc and dac devices, and lcds. the i 2 c minimizes interconnections betw een devices and is a synchronous, multi-master bus that allows additional devices to be connected and still handle system expansion and deve lopment. the bus includes collision detection and arbitrati on to prevent data corruption if two or more masters attempt to simultaneously control the i 2 c. the i 2 c module is driven by the peri pheral bus clock (typically 24 mh z) and the scl bit clock is generated from a prescaler. the pr escaler divide ratio can be pr ogrammed from 61,440 to 160 (decimal) which gives a maximum bit clock of 150 kbps. the i 2 c module supports the following features: ? two-wire (sda and scl) interface ? multi-master operation ? master or slave mode ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? acknowledge bit generation/detection ? bus busy detection ? software-programmable bit clock frequency up to 150 kbps ? software-selectable acknowledge bit ? on-chip filtering for spikes on the bus
mc13224v product preview, rev. 1.7 20 freescale semiconductor 4.6 serial peripheral interface (spi) modules the mc13224v has two spi modules that use a common architecture 4.6.1 external spi module the mc13224v offers a dedicated seri al peripheral interface (spi) module for external use. the spi is a high-speed synchronous serial data in put/output port used for interfacing with serial memories, peripheral devices, or other processors. the spi allows a serial bit stream of a programmed length (1 to 32 bits) to be shifted simultaneously into and out of the device at a progr ammed bit-transfer rate (called 4-wire mode). there are four pins associated with the spi port (spi_sck, spi_mosi, spi_miso, and spi_ss). the spi module can be programmed for master or slav e operation. it also supports a 3-wire mode where for master mode the mosi becomes momi, a bidire ctional data pin, and fo r slave mode the miso becomes siso, a bidirec tional data pin. in 3-wire mode, data is onl y transferred in one direction at a time. the spi bit clock is derived from the peripheral reference clock (typi cally 24 mhz with a maximum of 26 mhz). a prescaler divides the peri pheral reference clock with a progr ammed divide ratio from 2 to 256. typical bit clock range will be from 12 mhz to 93.75 khz. the spi has the following features: ? master or slave mode operation ? data buffer is 4 bytes (32 bits) in length ? spi transfer length program mable from 1 to 32 bits ? msb-first shifting ? programmable transmit bit rate (typically 12 mhz max) ? serial clock phase and polarity options ? full-duplex (4-wire) or bidire ctional data (3-wire) operation ? spi transaction can be polled or interrupt driven ? slave select signal ? low power (spi master uses ga ted clocks. spi slave clock deri ved completely from spi_sck.) 4.6.2 spi flash module (spif) the spif is an internal spi block de dicated to control, reading, and wr iting of the serial flash memory (nvm). it uses the same ar chitecture as the general spi block, but wi ll be limited by the characteristics of the flash spi interface.
mc13224v product preview, rev. 1.7 freescale semiconductor 21 4.7 synchronous serial interface (ssi) module the mc13224v provides a versatile sync hronous serial interface (ssi) whic h is a full-duplex, serial port that allows communication with a va riety of serial devices. these seri al devices can be digital signal processors (dsps), mcus, periphera ls, popular industry audio codecs, and devices that implement the inter-integrated circuit sound bus standard (i 2 s). the ssi typically transfers samples in a periodic manne r and it consists of i ndependent transmitter and receiver sections with common cloc k generation and frame synchronization. the external signals include the bit clock (ssi_bitck), frame s ync (ssi_fsyn), rx data (ssi_rx) , and tx data (ssi_tx). the ssi has the following basic operating m odes all with synchronous protocol: ? normal mode ? the simplest ssi mode transfers data in one time slot per frame ? network mode ? creates a time division mult iplexed (tdm) network, such as a tdm codec network or a network of dsps ? gated clock mode ? connects to spi-type inte rfaces on mcus or external peripheral chips with its multi-modes, the ssi can be pr ogrammed for two very useful functions: ? a second spi port augmen ting the mc13224v spi module ?i 2 s interface - the ssi is capable of generating the required clock fr equencies and data format to drive a serial stereo audio dac the ssi includes the following features: ? synchronous transmit and receive s ections with shared internal/e xternal clocks and frame syncs operating in master or slave mode ? normal mode operation using frame sync ? network mode operation allowing mu ltiple devices to share the port with as many as thirty-two time slots ? gated clock mode opera tion requiring no frame sync ? transmit and receive fifos. each of the fifos is 8x24 bits. th e tx/rx fifos can be used in network mode to provide 2 independent channels for transmission and reception ? programmable data interface modes such as i 2 s, lsb, msb aligned ? programmable word length (8, 10, 12, 16, 18, 20, 22 or 24 bits) ? program options for frame sync and clock generation ? programmable i 2 s modes (master, slave or normal). ov ersampling clock available as output in i 2 s master mode ? external ssi_bitclk input for use in i 2 s master mode. programmable oversampling clock of the sampling frequency available as output in master mode, when operated in sync mode ? programmable internal clock divider ? time slot mask registers for reduced cpu overhead (for both tx and rx) ? ssi power-down feature
mc13224v product preview, rev. 1.7 22 freescale semiconductor 4.8 analog-to-digital converter (adc) module the mc13224v adc module provides two 12-bit anal og-to-digital converters (adc1 and adc2) with 8 external channels (adc7 - adc0) that can be multiplexed to ei ther adc. adc1 can also sample the battery voltage for monitoring purposes. external pins (adc2_v refh, adc2_vrefl, adc1_vrefh, and adc1_vrefl) are provided for independent adc re ference voltages. the mi nimum sample time is 20 us. figure 8 shows a block diagra m of the adc module. each adc can be programmed to scan multiple select ed channels on a timed basis. the primary clock to the adc module is the peripheral reference clock (t ypically 24 mhz). for the ti me period between scan sequences, the primary clock is first divided by an 8-bit pres cale (1-255), and the de rived clock drives both the 32-bit delay timer and the adc sequencer. ea ch adc has its own delay timer and sequencer. once a scan sequence has been initiated, all selected channels can be sampled. registers are provided to define thresholds that can be enab led for the sampled channels. a thres hold can be assigned to a specific channel and can be programmed to be a less-than or greater-than threshold. multiple thresholds can be assigned to a single channel. warm -up of the analog portion of the ad c circuitry is provided for power management, and a separate 300 khz adc cloc k must be programmed via its own divider. the battery monitor has two (2) dedicat ed threshold registers to set the high and low limits of the battery sample channel. sample values are stored in a 8x16-bit fifo. the fifo accumulates samples from both adcs, and the 12-bit sample value and a 4-bit channel tag are saved fo r each sample. the fifo is read by the cpu from a register address. the module can be programmed to interrupt the pro cessor based on the timed sample activity. sample activity, sequencer activity, or fifo ?fullness? can all be enab led to generate an interrupt. the adcs can also be overridden to sample on comm and as opposed to sequencer, time-based activity.
mc13224v product preview, rev. 1.7 freescale semiconductor 23 figure 8. adc module block diagram the adc has the following features: ? 12 bit resolution ? separate input voltage ranges: vrefh to vrefl. max input of 3.6 vdc. min input of 0.0 vdc ? typical resolution of 10.5 bits ? conversion rate has a minimum sample time of 20us. effective number of bits varies with sample rate. ? 8-bit prescaler to provide the time base for the 32-bit timers ? two independent channels, each with a 32-bit timer ? simultaneous channel sampling or seque ntial channel sampling with dual adcs ? on-board battery detect sample channel ? primary adc has 9 channels. 8 exte rnal channels plus battery detect ? secondary adc has 8 external channels ? active channels for each adc are programmable ? a maximum of 8 active monitors can generate a interrupt request ? a 8-deep fifo for recording data ( 12-bit sample plus 4-bit channel tag) ? interrupt requests can be generated by the channel compare values, end-of-scan sequence, out-of-range, fifo stat us, and 32-bit timers ? independent soft reset m u x m u x analog channels adc0 - adc7 battery adc1 adc2 fifo (8 x 16-bit, 12-bit value + 4- bit channel tag) control registers divider m u x control override mode sequencer 2 m u x control override mode sequencer 1 compare mcu data bus prescaler analog adc2 mux sel adc1 mux sel adc1 enable adc2 enable adc clock adc clock 32-bit timer 32-bit timer peripheral reference clock 300 khz
mc13224v product preview, rev. 1.7 24 freescale semiconductor 5 pin assignments and connections figure 9. mc13224v pinout (top view; active bottom pads shown) notes: 1. only active substrate bottom pads are shown. 2. additional substrate pads (see mechanical drawings) no connect and are for mechanical attach only. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 mc13224v adc1 adc0 adc3 adc2 adc5 adc4 adc7_rtck adc6 tdi tdo tms tck uart2_cts uart2_rts uart2_tx uart2_rx xtal_32_in xtal_32_out vbatt rf_pll_flt coil_bk lreg_bk_fb kbi_1 kbi_0_hst_wk kbi_3 kbi_2 kbi_5 kbi_4 kbi_7 kbi_6 ssi_rx ssi_tx uart1_rts uart1_cts uart1_rx uart1_tx i2c_sda i2c_scl tmr3 tmr2 tmr1 tmr0 spi_sck spi_mosi spi_miso spi_ss ssi_bitck ssi_fsyn pa_pos pa_neg tx_on resetb xtal_24_in xtal_24_out rf_rx_tx rx_on rf_gnd ant_2 ant_1 rf_bias adc2_vrefh adc1_vrefh adc1_vrefl adc2_verfl 102 75 76 substrate gnd pads 103 111 112 113 114 120 121 122 124 129 130 131 133 123 132 77 78 79 84 85 86 87 88 93 94 95 96 97 104 105 106 115
mc13224v product preview, rev. 1.7 freescale semiconductor 25 5.1 pin definitions table 2 details the mc13224v pinout and functionality. table 2. pin function description pin # pin name type description 1 functionality 1 adc0 analog input or digital input/output adc analog input channel 0 / gpio30 adc sample channel can be used by either adc1 or adc2. 2 adc1 analog input or digital input/output adc analog input channel 1/ gpio31 adc sample channel can be used by either adc1 or adc2. 3 adc2 analog input or digital input/output adc analog input channel 2/ gpio32 adc sample channel can be used by either adc1 or adc2. 4 adc3 analog input or digital input/output adc analog input channel 3/ gpio33 adc sample channel can be used by either adc1 or adc2. 5 adc4 analog input or digital input/output adc analog input channel 4/ gpio34 adc sample channel can be used by either adc1 or adc2. 6 adc5 analog input or digital input/output adc analog input channel 5/ gpio35 adc sample channel can be used by either adc1 or adc2. 7 adc6 analog input or digital input/output adc analog input channel 6/ gpio36 adc sample channel can be used by either adc1 or adc2. 8 adc7_rtck analog input or digital input/output adc analog input channel 7 / return clock / gpio37 adc sample channel can be used by either adc1 or adc2. alternately, the signal returns tck for jtag to support adaptive clocking. 9 tdo digital input/output jtag test data output / gpio49 jtag debug port serial data output. 10 tdi digital input/output jtag test data input / gpio48 jtag debug port serial data input. 11 tck digital input/output jtag test clock input / gpio47 jtag debug port clock input. 12 tms digital input/output jtag test mode select input / gpio46 jtag debug port test mode select input. 13 uart2_rts digital input/output uart2 request to send input / gpio21 uart2 rts control input. 14 uart2_cts digital input/output uart2 clear to send output / gpio20 uart2 cts control output. 15 uart2_rx digital input/output uart2 rx data input / gpio19 uart2 receive data input. 16 uart2_tx digital input/output uart2 tx data output / gpio18 uart2 transmit data output.
mc13224v product preview, rev. 1.7 26 freescale semiconductor 17 uart1_rts digital input/output uart1 request to send input / gpio17 uart1 rts control input. 18 uart1_cts digital input/output uart1 clear to send output / gpio16 uart1 cts control output. 19 uart1_rx digital input/output uart1 rx data input / gpio15 uart1 receive data input. 20 uart1_tx digital input/output uart1 tx data output / gpio14 uart1 transmit data output. 21 i2c_sda digital input/output i 2 c bus data / gpio13 i 2 c bus signal sda 22 i2c_scl digital input/output i 2 c bus clock / gpio12 i 2 c bus signal scl 23 tmr3 digital input/output timer 3 io signal / gpio11 pin is used as counter output or counter input clock. 24 tmr2 digital input/output timer 2 io signal / gpio10 pin is used as counter output or counter input clock. 25 tmr1 digital input/output timer 1 io signal / gpio9 pin is used as counter output or counter input clock. 26 tmr0 digital input/output timer 0 io signal / gpio8 pin is used as counter output or counter input clock. 27 spi_sck digital input/output spi port clock / gpio7 spi port clock. 28 spi_mosi digital input/output spi port mosi/ gpio6 spi port master out slave in (mosi) data signal. 29 spi_miso digital input/output spi port miso / gpio5 spi port master in slave out (miso) data signal. 30 spi_ss digital input/output spi port ss / gpio4 spi port slave select (ss) signal. 31 ssi_bitck digital input/output ssi bit clock / gpio3 ssi serial tx/rx clock and is bi-directional. 32 ssi_fsyn digital input/output ssi frame sync / gpio2 ssi frame sync for data (rx or tx) and is bi-directional. 33 ssi_rx digital input/output ssi rx data input / gpio1 ssi serial rx data input. 34 ssi_tx digital input/output ssi tx data output / gpio0 ssi serial tx data output. 35 kbi_7 digital input/output keyboard interface bit 7 / gpio29 asynchronous interrupt input. 36 kbi_6 digital input/output keyboard interface bit 6 / gpio28 asynchronous interrupt input. table 2. pin function description (continued) pin # pin name type description 1 functionality
mc13224v product preview, rev. 1.7 freescale semiconductor 27 37 kbi_5 digital input/output keyboard interface bit 5 / gpio27 asynchronous interrupt input. 38 kbi_4 digital input/output keyboard interface bit 4 / gpio26 asynchronous interrupt input. 39 kbi_3 digital input/output keyboard interface bit 3 / gpio25 used as output for keyboard interface. 40 kbi_2 digital input/output keyboard interface bit 2 / gpio24 used as output for keyboard interface. 41 kbi_1 digital input/output keyboard interface bit 1 / gpio23 used as output for keyboard interface. 42 kbi_0_hst _wk digital input/output keyboard interface bit 0 / host walk-up output / gpio22 used as output for keyboard interface / alternative function as a wake-up output (based on a timer) to external device. 43 coil_bk power switch output buck converter coil drive output onboard buck converter connection to external coil, driven by onboard mosfet. 44 lreg_bk_fb power input voltage input to onboard regulators, buck regulator feedback voltage ? when using onboard buck converter, connect to load side of coil. ? when not using buck converter, connect to vbatt. 45 vbatt power input high side supply voltage to buck regulator switching mosfet and io buffers connect to battery. 46 rf_pll_flt analog voltage pll filter connection ? connection for pll filter (type 2, 2nd order) when using primary crystal with frequency other than 24 mhz (13-26 mhz). ? no connect for 24 mhz crystal. 47 xtal_32_in analog input optional 32.768 khz crystal oscillator input connect to 32.768 khz crystal 48 xtal_32_out analog output optional 32.768 khz crystal oscillator output connect to 32.768 khz crystal 49 xtal_24_out analog output primary 24 mhz crystal oscillator output ? connect to 13-26 mhz crystal (24 mhz default). ? no load capacitor required ? do not load with any capacitance. 50 xtal_24_in analog input primary 24 mhz crystal oscillator input ? connect to 13-26 mhz crystal (24 mhz default). ? no load capacitor required ? do not load with any capacitance. 51 resetb digital input system reset input active low, asynchronous reset 52 tx_on digital input/output control output for external rf component / gpio44 programmable control pin table 2. pin function description (continued) pin # pin name type description 1 functionality
mc13224v product preview, rev. 1.7 28 freescale semiconductor 53 pa_neg rf output rf power amplifier (pa) ouput negative ? open drain. must be connected to rf_bias through a bias network. ? only used for external dual port operation. ? do not use for single port operation. no connect. 54 pa_pos rf output rf power amplifier (pa) ouput positive ? open drain. must be connected to rf_bias through a bias network. ? only used for external dual port operation. ? do not use for single port operation. no connect. 55 rf_bias analog power output analog vdd regulator output when using dual port operation, tie to pa_pos and pa_neg through bias networks. 56 ant_1 digital input / output control output for external rf component / gpio42 programmable control pin. 57 ant_2 digital input / output control output for external rf component / gpio43 programmable control pin. 58 rf_gnd power input rf ground. connect to ground vss. 59 rx_on digital input / output control output for external rf component / gpio45 programmable control pin. 60 rf_rx_tx rf input/output rf single-ended, single port input and ouput ? interfaces to onboard balun. 50 impedance ? full bidirectional port with onboard t/r switch. ? used as single-ended rf input port for dual port operation with pa_neg and pa_pos pa outputs. 61 adc2_vrefl analog input or digital input / output low reference voltage for adc2 / gpio39 vrefl for adc2. 62 adc1_vrefl analog input or digital input / output low reference voltage for adc1 / gpio41 vrefl for adc1. 63 adc1_vrefh analog input or digital input / output high reference voltage for adc1 / gpio40 vrefh for adc1. 64 adc2_vrefh analog input or digital input / output low reference voltage for adc2 / gpio38 vrefh for adc2. 75-79 vss power input external package gnd pads. common vss. connect to ground. 84-88 vss power input external package gnd pads. common vss. connect to ground. 93-97 vss power input external package gnd pads. common vss. connect to ground. table 2. pin function description (continued) pin # pin name type description 1 functionality
mc13224v product preview, rev. 1.7 freescale semiconductor 29 102 mdo01 digital input/output message data out bit 1 output / gpio52 nexus debug port message data output bit 1. 103 mdo00 digital input/output message data out bit 0 output / gpio51 nexus debug port message data output bit 0. 104- 106 vss power input external package gnd pads. common vss. connect to ground. 111 mdo03 digital input/output message data out bit 3 output / gpio54 nexus debug port message data output bit 3. 112 mdo02 digital input/output message data out bit 2 output / gpio53 nexus debug port message data output bit 2. 113 mseo1_b digital input/output message start / end out bit 1 output / gpio60 nexus debug port message start / end output bit 1. signal is active low. 114 mseo0_b digital input/output message start / end out bit 0 output / gpio59 nexus debug port message start / end output bit 0. signal is active low. 115 vss power input external package gnd pads. common vss. connect to ground. 120 mdo05 digital input/output message data out bit 5 output / gpio56 nexus debug port message data output bit 5. 121 mdo04 digital input/output message data out bit 4 output / gpio55 nexus debug port message data output bit 4. 122 rdy_b digital input/output ready output / gpio61 nexus debug port ready output. signal is active low. 123 evto_b digital input/output event out output / gpio62 nexus debug port event out output. signal is active low. 124 dig_reg digital power output digital core logic vdd supply. 1.2 vdc internally regulated vdd supply to digital logic core. no connect,. for test only 129 mdo07 digital input/output message data out bit 7 output / gpio58 nexus debug port message data output bit 7. 130 mdo06 digital input/output message data out bit 6 output / gpio57 nexus debug port message data output bit 6. 131 mcko digital input/output message clock out output / gpio50 nexus debug port message clock output. 132 evti_b digital input/output event in input / gpio63 nexus debug port event in input. signal is active low. table 2. pin function description (continued) pin # pin name type description 1 functionality
mc13224v product preview, rev. 1.7 30 freescale semiconductor 5.2 hardware development interface interconnects the mc13224v supports two deve lopment hardware interfaces. 5.2.1 arm jtag interface connector the mc13224v supports connection to a subset of the defined arm jtag connector. the jtag hardware interface uses a 20-pin head er with a standard 0.1 inch spacing. table 3 shows how the mc13224v pins are connected to the associated jtag header pinouts if the jtag connect or is provided on the application. 133 nvm_reg nvm power output flash (nvm) vdd supply. vdd supply to flash. typically no connect . can be connected to vdd when regulated 1.8vdc mode is used. 65-74, 80-83, 89-92, 98-101, 107-110, 116-119, 125-128, 134-145 nc no connect these pads are provided for extra mechanical attach strength to meet demanding requirements of drop tests. 1 pins described as gpio have an alternative general purpose i/o function. table 3. arm jtag 20-pin connector assignments name 1 1 nc = no connect. pin # pin # name vbatt 1 2 vbatt nc 2 2 mc13224v does not support separate jtag reset trst. 34gnd tdi 5 6 gnd tms 7 8 gnd tck 9 10 gnd rtck 11 12 gnd tdo 13 14 gnd reset 3 3 vbatt through a 100k- pullup. 15 16 gnd nc 17 18 gnd nc 19 20 gnd table 2. pin function description (continued) pin # pin name type description 1 functionality
mc13224v product preview, rev. 1.7 freescale semiconductor 31 5.2.2 nexus mictor interface connector the mc13224v also supports connection to a subset of the defined nexu s mictor connector. the hardware interface is a 38-pin mi ctor target connector. table 4 shows the device pins th at are connected to the associated mictor pin outs if the mictor connector is used. table 4. nexus 38-pin mictor connector assignments name 1 1 nc means no connect. pin # pin # name nc 1 2 nc nc 3 4 nc nc 5 6 rtck nc 7 8 nc vbatt(pullup) 2 2 vbatt through a 100k- pullup. 9 10 evti_b tdo 11 12 vbatt 3 3 vbatt isolated by a 1k- resistor. nc 13 14 rdy_b tck 15 16 mdo07 tms 17 18 mdo06 tdi 19 20 mdo05 reset 4 4 vbatt through a 100k- pullup. 21 22 mdo04 nc 23 24 mdo03 nc 25 26 mdo02 nc 27 28 mdo01 nc 29 30 mdo00 nc 31 32 evto_b nc 33 34 mcko nc 35 36 mseo1_b nc 37 38 mseo0_b
mc13224v product preview, rev. 1.7 32 freescale semiconductor 6 system electrical specification this section details maximum ratings for the 99-pin lga package and recommended operating conditions, dc characteristics , and ac characteristics. 6.1 lga package maximum ratings absolute maximum ratings are stress ratings only, and functional opera tion at the maximu m rating is not guaranteed. stress beyond th e limits specified in table 5 may affect device reliability or cause permanent damage to the device. for functiona l operating conditions, refer to the re maining tables in this section. this device contains circuitry protect ing against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be ta ken to avoid application of any voltages higher than maximum-rated voltages to this high- impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v batt ) or the programmable pull-up resistor associated w ith the pin is enabled. table 5 shows the maximum ratings for the 99-pin lga package. table 5. lga package maximum ratings rating symbol value unit maximum junction temperature t j 125 c storage temperature range t stg -55 to 125 c moisture sensitivity level msl3-260 reflow soldering temperature (for reflow soldering profile and other lga module reference information, see freescale application note, an3311) 250 c power supply voltage v batt , v ddint -0.3 to 3.7 vdc digital input voltage vin -0.3 to (v ddint + 0.2) vdc rf input power p max 10 dbm instantaneous maximum current (single pin limit) i d tbd ma note: maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the limits in the electrical characteristics or recommended operating conditions tables. note: meets human body model (hbm) = 2 kv. rf input/output pins have no esd protection.
mc13224v product preview, rev. 1.7 freescale semiconductor 33 6.2 recommended oper ating conditions 6.3 dc electrical characteristics table 6. recommended operating conditions characteristic symbol min typ max unit power supply voltage single un-regulated source (vbatt and lreg_bk_fb tied common to v dd ) single regulated source (vbatt, lreg_bk_fb, and nvm_reg tied common to v dd ) onboard buck with un-regulated source (vbatt tied to v dd ) v dd 2.0 1.7 2.1 - 1.8 - 3.6 1.9 3.6 vdc vdc vdc input frequency f in 2.405 - 2.480 ghz operating temperature range t a -40 25 +105 c logic input voltage low v il 0 - 30% v batt v logic input voltage high v ih 70% v batt -v batt v rf input power p max --10dbm crystal reference oscillator frequency (40 ppm over operating conditions to meet the 802.15.4 standard.) f ref 13 24 26 mhz table 7. dc electrical characteristics (vbatt, lreg_bk_fb = 3.3 v, t a = 25 c, unless otherwise noted) characteristic symbol min typ max unit power supply voltage 1 (voltage applied to power input pins) vbatt (pin 45) lreg_bk_fb (pin 44) nvm_reg (pin 133) v dd 1.7 1.7 1.7 2.7 2.7 1.8 3.6 3.6 1.9 vdc vdc vdc high impedance (off-state) leakage current (per pin) ( v in = v dd or v ss , all input/outputs, device must not be in low power mode) |i oz |--1.0 a input current (v in = 0 v or v ddint ) ( v in = v dd or v ss , all input/outputs, device must not be in low power mode) i in --1.0a input low voltage (all digital inputs) v il 0-30% v batt v input high voltage (all digital inputs) v ih 70% v batt -v batt v input hysteresis (all digital inputs) v hys 0.06 v dd ? v
mc13224v product preview, rev. 1.7 34 freescale semiconductor 6.4 supply current characteristics internal pullup and pulldown resistors 2 (all port pins and irq) r pu -70- kohm maximum total i oh for all port pins |i oht |? tbdma output high voltage (i oh = -5 ma) (all digital outputs) v oh 80% v batt -v batt v output low voltage (i ol = 5 ma) (all digital outputs) v ol 0-20% v batt v maximum current in/out per io pin ? tbd ma maximum total i ol for all io pins i olt ?tbdma input capacitance (all non-supply pins) c in ?3?pf 1 maximum usable range of the reference voltage supply pin. this range may be modified because of the power supply configuration used in an application. see table 6 , ?power supply voltage?. 2 measurement condition fo r pull resistors: v in = v ss for pullup and v in = v dd for pulldown. table 8. supply current characteristics (vbatt, lreg_bk_fb = 3.3 v, t a = 25 c, unless otherwise noted) characteristics symbol min typ max unit off current - device is in reset condition (held in reset) and all gpio at ground. 0.3 a hibernate current - ram retained (8k, 32k, 64k, or 96k) 2khz onboard oscillator or 32 khz crystal oscillator cpu off (stop mode) wake-up from rti timer, or external request radio off adcs not available 8 kbyte ram retention 32 kbyte ram retention 64 kbyte ram retention 96 kbyte ram retention 1.1 - 3 5 a a a a doze current - ram retained (8k, 32k, 64k, or 96k) onboard 24 mhz oscillator on (high frequency accuracy) cpu off (stop mode) radio off adcs available, but inactive 8 kbyte ram retention 32 kbyte ram retention 64 kbyte ram retention 96 kbyte ram retention 60 - 65 70 a a a a table 7. dc electrical characteristics (continued) (vbatt, lreg_bk_fb = 3.3 v, t a = 25 c, unless otherwise noted) characteristic symbol min typ max unit
mc13224v product preview, rev. 1.7 freescale semiconductor 35 idle current - all ram active reference oscillator on (24 mhz) at 1.2 vdc cpu on at 1 mhz reference clock available to all peripherals radio off adcs available, but inactive 750 900 a run current - all ram active reference oscillator on (24 mhz) at 1.2 vdc cpu on at reference frequency radio off reference clock available to all peripherals adcs available, but inactive 3.3 5.0 ma receive current - all ram active reference oscillator on (24mhz) at 1.2 vdc radio rx on (receiving data) reference clock available to all peripherals adc1 available, but inactive cpu on at 2 mhz (dcd) cpu on at 2 mhz (ncd) 21 24 24 27 ma transmit current - all ram active reference oscillator on (24mhz) at 1.2 vdc radio tx on (sending data @ 0 dbm) reference clock available to all peripherals adcs available, but inactive cpu clock at 2 mhz (< 20% evm) @ 25 c 28 33 ma spi current - spi active - ma uart current - uart active - ma ssi current - - ssi active - ma adc current - adc active - ma timer current - timer active - ma i 2 c current - i 2 c active - ma table 8. supply current characteristics (continued) (vbatt, lreg_bk_fb = 3.3 v, t a = 25 c, unless otherwise noted) characteristics symbol min typ max unit
mc13224v product preview, rev. 1.7 36 freescale semiconductor 6.5 rf ac electrical characteristics table 9. receiver ac electrical charac teristics for 802.15.4 modulation mode (vbatt, lreg_bk_fb = 3.3 v, ta = 25 c, fref = 24 mhz, unless otherwise noted.) characteristic symbol min typ max unit sensitivity for 1% packet error rate (per) 1 (+25 c, @ package interface; die sensitiv ity is ~1db greater) non-coherent differential chip detection (dcd) non-coherent detection (ncd) 1 the digital modem contains a block desig nated as the rx modem. the rx modem can operate in: 1) non-coherent differential chip detection (dcd) mode which has 3-4db m less sensitivity but requires 3-4ma less receiver current, and 2) non-coherent detection (ncd) mode which has 3-4dbm greater sensit ivity but requires 3-4ma greater receiver current. - - -96 -100 -91 -95 dbm saturation (maximum input level) sens max -10-dbm channel rejection for 1% per (desired signal -82 dbm) +5 mhz (adjacent channel) -5 mhz (adjacent channel) +10 mhz (alternate channel) -10 mhz (alternate channel) >= 15 mhz - - - - - 40 40 57 57 65 35 35 50 50 60 db frequency error tolerance - - 200 khz symbol rate error tolerance - 120 80 ppm table 10. transmitter ac electrical ch aracteristics for 802.15.4 modulation mode (vbatt, lreg_bk_fb = 3.3 v, t a = 25 c, f ref = 24 mhz, unless otherwise noted.) characteristic symbol min typ max unit nominal output power 1 1 register sets output power to nominal (0 dbm typical). p out -0-dbm maximum output power 2 (evm < 20%) 2 register sets output power to maximum. -+5-dbm error vector magnitude p out @ -30 dbm p out @ 0 dbm p out @ +4 dbm evm - - 7 12 16 -% output power control range - 35 - db over the air data rate - 250 - kbps 2nd harmonic 3 3 measurements taken at output of evaluation circuit set for maximum power out and averaged over 100ms. --55-dbm/mhz 3rd harmonic 3 - - 64 - dbm/mhz spurious emissions 30-1000 mhz 1-12.75ghz - - db db nominal impedance (rf_rx_tx) 50 ohm
mc13224v product preview, rev. 1.7 freescale semiconductor 37 6.6 crystal reference clock oscillator characteristics figure 10. reference oscillator model table 11. reference oscillator specifications characteristic symbol min typ max unit crystal frequency 13 24 26 mhz oscillator frequency tolerance @ 25 c 20 ppm oscillator frequency tolera nce over temperature range. 802.15.4 mode +/- 40 ppm equivalent series resistance esr 60 external load capacitance c lext none required (onboard) pf internal osc startup time (13 mhz - 26 mhz) 1 1 this is part of de vice wake-up time. 0.8 1.2 ms y1 crystal 2pf cstray reference oscillator 1pf 4pf 8pf 2pf 1pf 4pf 8pf osc_in osc_out 0-5pf with steps of 160 ff. 0-5pf with steps of 160 ff. cstray course tune[3:0] fine tune[4:0] 1 meg (nom) mc13224v 4pf course tune[4] 4pf c ourse tune[4] course tune[3:0] fine tune[4:0]
mc13224v product preview, rev. 1.7 38 freescale semiconductor 6.7 optional 32.768 khz crystal oscillator specifications figure 11. 32.768 khz oscillator model table 12. 32.768 oscillator specifications characteristic symbol min typ max unit crystal frequency 1 1 recommended crystal abracom corporation crystal part number abs25-32.768-12.5-b 32.768 khz frequency tolerance @ 25 c 20 ppm frequency tolerance over temperature 2 2 example; stability at -20c is: -0.034 x (25-[-20]) 2 = -68.8ppm. -0.034 0.006ppm / (25-t) 2 ppm load capacitance 11 12.5 13 pf equivalent series resistance (esr) 60 k shunt capacitance 1.35 pf tolerated drive level 1 w y1 crystal cl1 32.768 khz oscillator osc_in osc_out cl2 feedback mc13224v cstray1 cstray2
mc13224v product preview, rev. 1.7 freescale semiconductor 39 6.8 internal low speed reference oscillator specifications 6.9 control timing and cpu bus specifications 6.9.1 timer module input characteristics four-bit synchronizer circuits dete rmine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external s ource to the timer counter. these synchronizers operate from the peripheral clock rate. table 15 shows timer input timing values. table 13. internal 2 khz oscillator specifications characteristic symbol min typ max unit oscillator frequency tolerance over temperature 2 - khz frequency tolerance @ 25 c 2 - khz frequency accuracy after calibration - % temperature coefficient - %/ c supply voltage coefficient - %/v initial calibration time - ms table 14. mcu control timing (vbatt, lreg_bk_fb = 3.3 v, t a = 25 c, f ref = 24 mhz, unless otherwise noted.) parameter symbol min typical max unit cpu bus frequency (t cyc = 1/f bus )f bus f ref /64 1 1 normal operation uses a 24 mhz reference. the mc13224v allows up to a 26 mhz max reference oscillator. ?f ref 1 mhz cpu bus frequency with active tx or rx 2 mhz real-time interrupt internal oscillator frequency 2 khz external reset pulse width 2 2 this is the shortest pulse that is guara nteed to be recognized as a reset pin req uest. there always must be 3 clocks of the operating oscillator; this can vary from the lo w power oscillators to the reference oscillator. - 4 ? osc clks external minimum interrupt pulse width (kbi[7:4]) - - ? ns table 15. timer input timing (vbatt, lreg_bk_fb = 3.3 v, ta = 25 c, fref = 24 mhz, unless otherwise noted.) parameter symbol min max unit external clock frequency dc peripheral_bus_clk/3 mhz external clock period >3 ? t cyc input capture pulse width tbd ? t cyc
mc13224v product preview, rev. 1.7 40 freescale semiconductor 6.10 spi timing figure 12. spi timing diagram table 16 describes the timing require ments for the spi system. table 16. spi timing parameter symbol min typical max unit master spi_sck period t cyc peripheral_ bus_clk*2 38 peripheral_ bus_clk * 256 ns slave spi_sck period t cyc 10 ns slave spi_ss setup time t ss_su 10 ns slave spi_ss hold time t ss_h 10 ns slave spi_mosi setup time t si_su 10 ns slave spi_mosi hold time t si_h 10 ns master spi_miso setup time t mi_su 20 ns master spi_miso hold time t mi_h 0ns master spi_mosi output time t mo 5ns slave spi_miso output time (with 15 pf load) t so 20 ns spi_sck spi_mosi (slave in) spi_ss (slave in) spi_miso (master in) t xx_su t xx_h t cyc t ss_su t ss_h t mo, t so spi_mosi (master out) spi_miso (slave out)
mc13224v product preview, rev. 1.7 freescale semiconductor 41 6.11 ssi timing 6.12 i 2 c specifications table 17 describes the timing requirements for the i 2 c system. the i 2 c module is driven by the periphe ral bus clock (typicall y max 24 mhz) and the scl bit clock is generated from a prescaler. the pr escaler divide ratio can be pr ogrammed from 61,440 to 160 (decimal) which gives a maximum bit clock of 150 kbps. figure 13. i 2 c timing diagram note the i 2 c timing limits reflect values that are necessary meet to the i 2 c bus specification. table 17. i 2 c signal dc specifications (i2c_sda and i2c_scl) parameter symbol min typical max unit input low voltage v il -0.3 - 0.3 v ddint v input high voltage v ih 0.7 vbatt - vbatt + 0.3 v input hysteresis v hys 0.06 vbatt ? v output low voltage 1 (i ol = 5 ma) 1 sda and scl are open drain outputs v ol 0 - 0.2 vbatt v input current (v in = 0 v or v ddint )i in --1a pin capacitance c in <10 pf maximum current in/out per port pin ? tbd ma maximum total i ol for all port pins i olt ?tbdma sda scl t f t hd t low t r t hd;dat t su;dat t high t f ssr t su;sta t hd:sta p t r t buf s t su;sto
mc13224v product preview, rev. 1.7 42 freescale semiconductor table 18. i 2 c signal ac specifications 1 1 all values referred to v ihmin and v ilmax levels parameter symbol standard-mode fast-mode unit min max min max scl clock frequency (when source) f scl 0 100 0 150 khz hold time (repeated) start condition. after this period, the first clock pulse is generated t hd;sta 4.0 - 0.6 - s low period of the scl clock t low 4.7 - 1.3 - s high period of the scl clock t high 4.0 - 0.6 - s set-up time for a repeated start condition t su;sta 4.7 - 0.6 - s data hold time t shd;dat 0 2 2 a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. 3.45 3 3 the maximum t hd;dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 0 2 0.9 3 s data setup time t su:dat 250 - 100 4 4 a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat >= 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl sign al, it must output the next data bit to the sda line t r max + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. -ns rise time for both sda and scl signals t r - 1000 20 + 0.1c b 5 5 c b = total capacitance of one bus line in pf. if mixed with hs-mode devices, the faster fall-times are allowed. 300 ns fall time for both sda and scl signals t f - 300 20 + 0.1c b 5 300 ns bus free time between a stop and start condition t buf 4.7 - 1.3 - s capacitive load for each bus line c b - 400 - 400 pf
mc13224v product preview, rev. 1.7 freescale semiconductor 43 6.13 flash specifications 6.14 adc characteristics table 19. flash characteristics (ta = 25 c, fref = 24 mhz, unless otherwise noted.) characteristic symbol min typical max unit supply voltage for program/erase/read (with directly regulated supply) v prog/erase 1.70 1.90 v spi clock frequency f fclk 13 mhz read current (13 mhz) 915ma program and erase current 10 15 ma standby current 210 a sector erase duration 75 ms block erase duration 75 ms chip erase duration 150 ms byte program duration 60 s program/erase endurance 100,000 cycles data retention t d_ret 100 ? years table 20. adc electrical ch aracteristic s (operating) (vbatt, lreg_bk_fb = 3.3 v, ta = 25 c, fref = 24 mhz, unless otherwise noted.) characteristic condition symbol min typical max unit adc supply current (per adc) enabled ? 2.65 - ma disabled ? 5 a reference potential, low v refl vss ? v refh v reference potential, high v refh v refl ? vbatt v analog input voltage 1 1 maximum electrical operating range, not valid conversion range. v indc v ss ? 0.2 ? v dd +0.2 v ?battery? input channel reference voltage 1.2 v table 21. adc timing/per formance characteristics characteristic symbol condition min typ max unit resolution 12 bits effective resolution 10.5 bits
mc13224v product preview, rev. 1.7 44 freescale semiconductor 7 developer environment the mc1322x family is supported by a full set of ha rdware/software evaluati on and development tools. 7.1 hardware development interfaces the arm debug environment suppo rts both a jtag debug interface an d an extended capability nexus interface. 7.1.1 jtag hardware debug port the jtag port is the simpler a nd more common debug por t for the arm core. a standard 20-pin connector as described in section 5.2.1, ?arm jtag interface connector? ?, is connected to the tdi, tms, tck, tdo, and rtck signals of the mc13224v . through the jtag serial interface, standard debug and development activi ties such as accessing memory and regi sters, control of the cpu, download of flash memory, and softwa re debug can be accomplished. 7.1.2 a7s nexus3 (nex) arm7 core development interface the development and debug environmen t of the arm7tdmi-s core is based on the a7s nexus3 interface (compliant with a class 3 device of the ieee-isto 5001 standard for real-time embedded system design). this interface allows expansion of the development features of the jtag port (through the addition of auxiliary signals, see section 5.2.2, ?nexus mict or interface connector? ). development features include: ? program trace via branch trace messaging (btm ). branch trace messaging displays program flow discontinuities (direct and i ndirect branches, exceptions, etc.), allowing the de velopment tool to interpolate what transpires between the discontinuities. thus static code may be traced. ? data trace via data write me ssaging (dwm) and data read messaging (drm). this provides the capability for the development t ool to trace reads and/or writes to (selected) internal memory resources. ? ownership trace via ownership trace messagi ng (otm). otm facilitates ownership trace by providing visibility of which process id or operating system task is activated. an ownership trace number of input channels 8 adc conversion clock frequency f adcclk --50khz conversion cycles (continuous convert) ccp 6 adcclk cycles conversion time t conv ?20 s input leakage current ? ? - na analog input voltage 1 v ain vdd v refl v refh v 1 analog input must be between v refl + 0.2 and v refh - 0.2 for valid conversion. table 21. adc timing/performance characteristics (continued) characteristic symbol condition min typ max unit
mc13224v product preview, rev. 1.7 freescale semiconductor 45 message is transmitted when a new process/task is activated, allowing the development tool to trace ownership flow. ? run-time access to the memory map via the jtag port. this allows for enhanced download/upload capabilities ? watchpoint messaging (wpm) via the auxiliary pins ? watchpoint trigger enable of pr ogram and/or data trace messaging ? auxiliary interface for higher data input/output ? registers for program trace, ownership trace , watchpoint trigger, and read/write access ? programmable processor st all function to mitigate message queue overrun risk ? all features controllable and configurable via the jtag port 7.2 software development tools an integrated development environment (ide) is av ailable to facilitate the development of embedded applications targeting the mc13224v plat form. features of the ide include: ? project management tools and code editor ? highly optimizing arm compiler supporting c and c++ ? extensive jtag and rdi debugger support ? run-time libraries including source code ? relocating arm assembler ? linker and librarian tools ? debugger with arm simulator, jtag suppor t and support for rtos-aware debugging on hardware ? rtos plug-ins available ? code templates for commonly used code constructs ? sample projects for evaluation boards ? user and reference guides, bot h printed and in pdf format ? context-sensitive online help the ide is complemented by the beekit ? wireless connectivity toolkit. b eekit is a stand alone software application targeting windows ? operating systems. beekit provides a graphical user interface (gui) in which users can create, modify, save , and update wireless networking solu tions. with the solution explorer property list windows, users can set configuration parameters to c ontrol the setup and execution behavior of the wireless link within their appl ication. the configurati on parameters can be va lidated inside beekit to ensure all values provided are within acceptable ranges prior to generation of a workspace. all this functionality provides a mechanism fo r developers to configure and va lidate their network parameters without having to navigate throu gh multiple source files to configure the same parameters. beekit supports freescale?s simple mac (smac), ie ee 802.15.4-compliant mac, and the freescale beestack ? .
mc13224v product preview, rev. 1.7 46 freescale semiconductor 7.3 development hardware several different development modules and kits will be av ailable to allow evalua tion of zigbee and ieee 802.15.4 applications. the modules will provide capabilities for coordi nator, router, and end device nodes. reference designs will be avai lable for rf design a nd low power applications including 2-layer and 4-layer pcbs. 8 preliminary mechanical diagrams (case 1901-01, non-jedec) figure 14. mechanical diagram (1 of 2)
mc13224v product preview, rev. 1.7 freescale semiconductor 47 figure 15. mechanical diagram bottom view (2 of 2)
document number: mc1322x rev. 1.7 06/2008 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064, japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only : freescale semiconductor lite rature distribution center p.o. box 5405 denver, colorado 80217 1-800-521-6274 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circui ts or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does freescale se miconductor assume any liability arising out of the application or use of any product or circuit, and sp ecifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor dat a sheets and/or specificat ions can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor d oes not convey any lice nse under its patent rights nor the rights of others. freescale semiconduc tor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other ap plications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal inju ry or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semico nductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against a ll claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale and the freescale logo are trademarks or registered trademarks of freescale semiconductor, inc. in the u.s. and other countr ies. all other product or service names are the property of their respective owners. arm is the registered trademark of arm limited. arm7tdmi-s is the trademark of arm limited.? freescale semiconductor, inc. 2005, 2006, 2007, 2008

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